With the increase in fabrication density over the last few decades, semiconductor technology is being pushed to extreme limits and power dissipation has become a major issue. Researchers have been looking for alternate technologies to address the issues. A fundamental lower bound in energy consumption was given by Landauer (Landauer, 1961), who postulated that at least kT ln 2 Joule of energy is dissipated as heat for every bit lost during some computation, where k is the Boltzmann constant and T is the absolute temperature of the environment. Also, Bennett (Bennett, 1973) argued that for energy consumption to be theoretically zero, the computation must be information lossless or reversible. These considerations primarily triggered a proliferation of research in reversible computing over the last two decades. Though there is no proven technology for implementing reversible logic, recent developments in quantum computing systems have made the area relevant again. We focus on the construction of parity-preserving reversible circuit modules in the context of this study. A reversible circuit module is said to be parity-preserving if the parity of the inputs (i.e., exclusive-OR of the input bits) is the same as the parity of the outputs. When evaluating alternate reversible logic implementations of given functions, the commonly used parameters are: (i) the number of reversible gates or gate count (GC), (ii) quantum cost (QC), (iii) the number of constant inputs (CI), and (iv) number of garbage outputs (GO).
In addition, we focus on multiplication design, which is a very important operation required in many applications. Several methods exist for implementing a digital multiplier. A common method involves computing a collection of partial products and afterward mixing them through binary adders to get the final result.
To solve the problems, a research team led by Wei SHI published their new research on 15 December 2024 in Frontiers of Computer Science co-published by Higher Education Press and Springer Nature.
In this study, our research team, suggests six parity-preserving reversible blocks (Z, F, A, T, S, and L) with improved quantum cost. The reversible blocks are synthesized using an existing synthesis method that generates a netlist of multiple-control Toffoli (MCT) gates. Various optimization rules are applied at the reversible circuit level, followed by transformation into a netlist of elementary quantum gates from the NCV library. The designs of full-adder and unsigned and signed multipliers are proposed using the functional blocks that possess parity-preserving properties. The proposed designs are compared with state-of-the-art methods and found to be better in terms of quantum cost, garbage output, constant input, and gate count.
Future studies will involve expanding our current efforts to incorporate our suggested reversible quantum-based multiplier circuit into the comprehensive complicated designs of other similar reversible quantum systems.
DOI: 10.1007/s11704-023-2492-3
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